The formation of connection sites on integrated circuits is well known. Conventional methods of forming connection sites are described, for example, in U.S. Pat. No. 6,117,299 (Rinne et al.) and U.S. Pat. No. 6,074,895 (Dery et al.).
With the growing complexity and increased numbers of transistors which can be placed on a single ULSI chip or die has come additional demands on the wiring and connection site processes. The number of internal metal layers required to interconnect the newer, more complex microprocessors has dramatically increased, as have the number of external connection sites. Due to the increased complexity, lower yield and added cost associated with the metallurgy, it is desirable to fabricate smaller semiconductor dies and place more wiring levels in the packaging. To accomplish this without degrading performance, a large number of exterior die connection sites are required.
One of the most efficient and compact ways for providing external die connection sites uses solder bumps in the so-called flip chip or C-4 (i.e., the Controlled Collapse Chip Connection) process. This technology eliminates the need to wire bond connections from the die bond pads to a packaging lead frame, and offers more connection sites, higher speeds, improved heat transfer, and can be used with smaller die sizes. Although C-4 technology is somewhat costly in terms of time, materials, and equipment, and although it presents certain environmental issues, the use of solder bumped integrated circuits is growing at a significant rate. At present, conventional large flip chip semiconductor dies may provide hundreds of connection sites.
The importance of this technology is underscored by the formation of the “MicroFab Consortium” (MicroFab) of private and governmental entities for the purpose of exploring and developing new methods for applying solder bumps and other materials to integrated circuit dies, optical circuits, hybrids, chip carriers and other devices. The literature suggests that MicroFab has successfully developed manufacturing prototypes of piezoelectrically actuated print heads for ejecting low-melting point solder balls of well-defined sizes at rates approaching several kilohertz (kHz). Although piezoelectric-based solder ball printers have several attractive characteristics, they are limited by the fact that piezoelectric device strength decreases rapidly with rising temperatures and vanishes at their Curie temperatures. The Curie temperatures of useful ceramics are well under 300° C. Thus, the ability to manipulate solder viscosity and surface tension by raising temperature is limited in such print heads. Other significant limitations to using piezoelectric-based print heads includes their complexity and the great difficulty in mass producing them in large, inexpensive, relatively light weight arrays.
Thus, a need exists for a method of forming a micro flip chip which contains a very high density of solder bumps, and to do so in a way which is not restricted by the Curie temperatures of the print head materials.